KFLOP has 8 hardware 8-bit PWMs (Pulse Width Modulators) that output on dedicated KFLOP JP6 pins
[[File:KFLOP_PWMS.png|none|link=]]
{
SetBitDirection(26,1); // define bit as an output
FPGA(IO_PWMS_PRESCALE) = 6564; // divide clock by 65 (1 KHz~1KHz)
FPGA(IO_PWMS) = 128; // square wave
FPGA(IO_PWMS+1) = 1; // Enable
SetBitDirection(26,1); // Set bit 26 (PWM 0 as an output)
SetBitDirection(DIR_BIT0,1); // Set bit 30 (Direction an output)
FPGA(IO_PWMS_PRESCALE) = 1; // set pwm period to 30 ~33 KHz
FPGA(IO_PWMS+1) = 1; // enable the PWM
{
SetBitDirection(26,1); // Set bit 26 (PWM 0 as an output)
FPGA(IO_PWMS_PRESCALE) = 1; // set pwm period to 30 ~33 KHz
FPGA(IO_PWMS+1) = 1; // enable the PWM