Configuring KFLOP for use with KStep

 

Configuring KStep is fairly straightforward as it is normally an open loop system (although it is possible to operate in closed loop stepper mode) so all feedback, servo, PID, Filter, Feedforward, commutation parameters are not used and amy be ignored.  KStep is basically a Step/Dir drive so it makes use of the Step/Dir Output mode in KFLOP.  See the items circled in red below.  Note output mode type "Step Dir" is selected.  Shown is the Output Channel selection for KStep Motor #0.  Note that output channel 8 is selected instead of 0 to select the LVTTL output mode required by KStep.  See here for more information.  Motors #0, #1, #2, and #3 would be selected as 8, 9, 10, 11 respectively.  Output gain may be specified as -1 to reverse the direction of motion.

 

Example Axis configurations are provided as KStepAxis0.mot, KStepAxis1.mot, KStepAxis2.mot, KStepAxis3.mot

 

 

 

Limit switch options may also be selected.  KStep 12-24V Opto inputs are commonly used as Limit switch inputs and are referenced as Input Bits 168-183.  Using NC type limit switches will mean that the inputs are normally high and go open and low when activated.  In this case the "Stop when low" option should be selected.   For more info see here.

 

 

Motion profile settings on the Step Response Screen are used

 

 

 

 

Enable KStep Amplifiers

 

An amplifier enable signal is required to enable the KStep Full Bridge Amplifiers.  One signal enables all 4 of the KStep amplifiers.  The enable signal is positive true meaning it requires a high level 3.3V LVTTL (sourcing) signal to enable the drives.  With the standard  JP36 26-pin ribbon connector to KFLOP this signal is connected to KFLOP IO 45 which must be set as an output and set high to enable the drives.    The enable signal is optically isolated from the KSTEP VBB and GND when operating KSTEP in isolated mode.

 

If JP36 is not used then a 3.3V enable signal may alternately be applied to a screw terminal on J6.  Or when two KSteps are stacked for driving 8 motors the screw terminals on J6 may be used as an output on the first KStep to daisy chain the enable signal to the second KStep.

 

For testing purposes KStep may be enabled using the Digital I/O Screen as shown below.

 

 

 

From C code the Amplifiers may be enabled with the code shown below.

 

      SetBitDirection(45,1);  // set Enable Signal as Output

      SetBit(45);             // Enable the KStep Amplifiers

 

 

Additionally, code might be added to enable the amplifiers as soon as motion is detected and disabled after a period of time with no motion.  Here is an example:

 

      double T0, LastX=0, LastY=0, LastZ=0;

      for (;;) // loop forever

      {

            WaitNextTimeSlice();

           

            // Service Amplifier disable after no activity for a while

            if (ch0->Dest != LastX || ch1->Dest != LastY || ch2->Dest != LastZ)

            {

                  // we moved - enable KStep Amplifers

                  SetBit(45);

                  T0 = Time_sec();  // record the time and position of last motion

                  LastX=ch0->Dest;

                  LastY=ch1->Dest;

                  LastZ=ch2->Dest;

            }

            else

            {

                  if (Time_sec() > T0 + 10.0) ClearBit(45);

            }

      }

 

 

 

 

 

Digital Status

 

The Opto Isolated 12-24V Digital Inputs can be observed by selecting the Virtual Tab of the Digital I/O Screen.  The 16 opto inputs will be shown as active when current is flowing through the opto circuit.  For input circuit and pinouts see.  The KStep Opto Inputs are actually virtual inputs that are multiplexed in through KFLOP I/O.  KFLOP can perform this multiplexing automatically by setting the global variable KStepPresent.  The following line of C code should be added to your Init.c program:

 

KStepPresent=TRUE;

 

 

 

 

Relay Driver Outputs

 

The Opto Isolated 24V outputs can be observed and controlled by selecting the KFLOP tab of the Digital I/O Screen.  The 2 opto outputs will be shown as active when the outputs are conducting current.  The KStep outputs are the same as the standard KFLOP outputs except they are opto isolated and amplified to handle up to 24V.  For output circuit and pinouts see.

 

 

 

To make use of the outputs within a C program the following C code shows an example of enabling both the outputs, turning them on, then turning them off.

 

 

      SetBitDirection(0,1);  //set as output

      SetBitDirection(1,1);  //set as output

     

      SetBit(0);  // turn output on

      SetBit(1);  // turn output on

 

      ClearBit(0);  // turn output off

      ClearBit(1);  // turn output off

 

 

 

Analog Output

 

The KStep Analog output is a low Speed (10ms time constant) isolated analog output that is commonly used as a VFD Spindle Speed Control signal.  KFLOP outputs a 3.3V digital PWM on IO 44 to KSTEP which optically isolates and filters it to create an analog signal.  Isolated power and ground (often supplied by the VFD) are required.  The analog output voltage will be a proportion of the supplied voltage relative to the duty cycle of the PWM signal.  For example a 75% high duty cycle will provide a voltage which is approximately 75% of the supplied voltage.

 

To configure KFLOP to output the appropriate PWM signal into KSTEP the configuration code below should be used.  There is an FPGA option to move PWM0 (which normally is output on connector JP6 with the other 7 PWM outputs) over to JP7 Pin5 IO44.  IO44 must also be configured as an output, the PWM Prescale Divider set to a reasonable value, and the PWM enabled.

 

 

      FPGA(KAN_TRIG_REG)=4;  // Mux PWM0 to JP7 Pin5 IO 44 for KSTEP

      SetBitDirection(44,1);  // define bit as an output

      FPGA(IO_PWMS_PRESCALE) = 46;        // divide clock by 46 (1.4 KHz)

      FPGA(IO_PWMS+1) = 1;                // Enable

 

The Analog output has nonlinearity near the 0% duty cycle region due to opto coupler pulse shaping effects.  The nonlinearity can be mostly corrected in software through calibration.  Below is a raw uncorrected analog output with a PWM frequency of 1.4KHz (PWM Prescale = 46).

 

 

 

Using a correction algorithm where the PWM value that will most closely produce the desired output voltage is determined from a table lookup approach for the first 7 PWM counts, and a simple linear interpolation is used for determining PWM settings 7 through 240 the linearized results are shown below. Although now linear there is still low resolution for settings below ~5% full scale.