KFLOP has 8 hardware 8-bit PWMs (Pulse Width Modulators) that output on dedicated KFLOP JP6 pins
[[File:KFLOP_PWMS.png|none|link=]]
{
SetBitDirection(26,1); // define bit as an output
FPGA(IO_PWMS_PRESCALE) = 6564; // divide clock by 65 (1 KHz~1KHz)
FPGA(IO_PWMS) = 128; // square wave
FPGA(IO_PWMS+1) = 1; // Enable
Usually a PWM is used to drive a Full H-Bridge Driver to control the effective voltage to a motor coil. There are two basic modes of operation: Sign/Magnitude and Anti-Phase. With Sign and Magnitude the Sign controls the polarity of voltage (either positive or negative) and the PWM pulse controls the fraction of time the voltage is applied. The voltage is applied for some fraction of the time period and zero volts are applied for the remainder. With Anti-phase there is no Direction Output required. Instead both positive and negative voltages are applied every cycle. Equal amounts of positive and negative voltage results in effectively zero volts. With KFLOP's 8-bit PWMs setting a PWM value of 128 will result in equal positive and negative times.
The KFLOP Axis Output Mode should be set to "NO Output" as your C Code will be performing the Output. The Max Output should be set to less than the maximum PWM range. Either 255 for Sign/Mag types or 127 for Anti-Phase types.
SetBitDirection(26,1); // Set bit 26 (PWM 0 as an output)
SetBitDirection(DIR_BIT0,1); // Set bit 30 (Direction an output)
FPGA(IO_PWMS_PRESCALE) = 1; // set pwm period to 30 ~33 KHz
FPGA(IO_PWMS+1) = 1; // enable the PWM
{
SetBitDirection(26,1); // Set bit 26 (PWM 0 as an output)
FPGA(IO_PWMS_PRESCALE) = 1; // set pwm period to 30 ~33 KHz
FPGA(IO_PWMS+1) = 1; // enable the PWM