GPIO - Open Drain?

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jtremel
Posts: 2
Joined: Fri Jun 21, 2019 10:55 pm

GPIO - Open Drain?

Post by jtremel » Fri Jun 21, 2019 11:08 pm

Is it possible to configure any of the I/0 pins to operate in open drain/collector mode when used as general purpose outputs?

I know that the Step/Dir pins on JP7 can indeed be open collector outputs when used as Step/Dir generators. I have not yet found a way to configure them in open collector mode when used as GP outputs though. Is there some FPGA option call - or some other way - to do this?

I have a couple of reasons for wanting to do this:
1) interfacing with the I/O (enable input, etc...) of particular motor drivers
2) Implementing a software I2C interface to interact with some external sensors that don't come with an SPI option.

Thanks,
Jim

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TomKerekes
Posts: 591
Joined: Mon Dec 04, 2017 1:49 am

Re: GPIO - Open Drain?

Post by TomKerekes » Sat Jun 22, 2019 1:35 am

Hi Jim,

To make a GP IO pin "open" configure it as an Input with SetBitDirection(X, 0);

Then to drive the IO pin low Clear the bit and configure it as an Output with ClearBit(x); SetBitDirection(X, 1);

HTH
Regards,

Tom Kerekes
Dynomotion, Inc.

jtremel
Posts: 2
Joined: Fri Jun 21, 2019 10:55 pm

Re: GPIO - Open Drain?

Post by jtremel » Sun Jun 23, 2019 9:39 pm

Hi Tom,

Thanks for the response. I will go down that path... I just didn't want to have to worry about any potential timing problems creating the chance of having both IC's driving the lines at different levels - creating a shorting condition.

Thanks,
Jim

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