GPIO - Open Drain?
Posted: Fri Jun 21, 2019 11:08 pm
Is it possible to configure any of the I/0 pins to operate in open drain/collector mode when used as general purpose outputs?
I know that the Step/Dir pins on JP7 can indeed be open collector outputs when used as Step/Dir generators. I have not yet found a way to configure them in open collector mode when used as GP outputs though. Is there some FPGA option call - or some other way - to do this?
I have a couple of reasons for wanting to do this:
1) interfacing with the I/O (enable input, etc...) of particular motor drivers
2) Implementing a software I2C interface to interact with some external sensors that don't come with an SPI option.
Thanks,
Jim
I know that the Step/Dir pins on JP7 can indeed be open collector outputs when used as Step/Dir generators. I have not yet found a way to configure them in open collector mode when used as GP outputs though. Is there some FPGA option call - or some other way - to do this?
I have a couple of reasons for wanting to do this:
1) interfacing with the I/O (enable input, etc...) of particular motor drivers
2) Implementing a software I2C interface to interact with some external sensors that don't come with an SPI option.
Thanks,
Jim